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CAR.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    20:52:36 06/25/2017 
+-- Design Name: 
+-- Module Name:    CAR - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity CAR is
+	port( clk, rst_n : in std_logic;
+			memIndex_input : in std_logic_vector(3 downto 0);
+			memIndex_output : out std_logic_vector(3 downto 0)
+			);
+end CAR;
+
+architecture Behavioral of CAR is
+	signal temp : std_logic_vector(3 downto 0):="0000";
+begin
+	process(clk, rst_n) begin
+	if rst_n = '0' then
+		temp <= "1111";
+	else
+		if rising_edge(clk) then
+			temp <= memIndex_input;
+		end if;
+	end if;
+	end process;
+	memindex_output <= temp;
+
+
+end Behavioral;
+

CZN.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    17:47:34 06/25/2017 
+-- Design Name: 
+-- Module Name:    CZN - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity CZN is
+	port(
+			clk : in std_logic;
+			cznWrite : in std_logic;
+			CZNin : in std_logic_vector(2 downto 0);
+			CZNout : out std_logic_vector(2 downto 0)
+			);
+end CZN;
+
+architecture behave of CZN is
+
+begin
+	process (clk) begin
+		if rising_edge(clk) then
+			if cznWrite = '1' then
+				CZNout <= CZNin;
+			end if;
+		end if;
+	end process;
+	
+end behave;
+

ControlMemory.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    20:53:57 06/25/2017 
+-- Design Name: 
+-- Module Name:    ControlMemory - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity ControlMemory is
+	generic (K: integer:=19; -- number of bits per word (data size)
+				W: integer:=4 -- number of address bits  (address size)
+			 ); 
+	port (
+		clk, rst_n : std_logic;
+		ADDR: in std_logic_vector (W-1 downto 0); -- RAM address
+		DOUT: out std_logic_vector (K-1 downto 0)); -- read data
+end ControlMemory;
+
+
+architecture behave of ControlMemory is
+
+	subtype WORD is std_logic_vector ( K-1 downto 0); -- define size of WORD
+	type MEMORY is array (0 to 2**W-1) of WORD; -- define size of MEMORY
+	signal RAM16: MEMORY; -- define RAM16 as signal of type MEMORY
+	
+	begin
+	process (clk, rst_n, ADDR, RAM16)
+	
+		variable RAM_ADDR_IN: integer range 0 to 2**W-1; -- to translate address to integer
+		--variable STARTUP: boolean :=true; -- temporary variable for initialization
+		
+		begin
+			if (rst_n = '0') then -- for initialization of RAM during start of simulation
+				RAM16 <= (0 =>   "0100010000000000011", -- initializes first 12 locations in Control Memory
+									1 => "0000001000000000001", -- to specific values
+									2 => "0000000110100000000", 
+									3 => "0000000110100100100", 
+									4 => "0000000110101000100",
+									5 => "0000000110101010100",
+									6 => "0000000000000001000",
+									7 => "0001000000000000010",
+									8 => "1010000000000000000",
+									9 => "0100000001100000000",
+									10 => "0101100000000000000",
+									11 => "0100000000110010100",
+									12 => "0100000000111000100",
+									others => "0000000000000000000"
+								);
+				DOUT <= "XXXXXXXXXXXXXXXXXXX"; -- force undefined logic values on RAM output
+			else
+				--if rising_edge(clk) then
+					RAM_ADDR_IN := conv_integer (ADDR); -- converts address to integer
+				--end if;
+				DOUT <= RAM16 (RAM_ADDR_IN);
+			end if;
+end process;
+
+end architecture behave;
+

Controller.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    20:19:14 06/25/2017 
+-- Design Name: 
+-- Module Name:    Controller - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+use ieee.std_logic_unsigned.all;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Controller is
+	port( clk, reset: in std_logic;
+			opcode: in std_logic_vector(3 downto 0);
+			pcSrc, pcWrite, pcWriteCond, IorD, MemWrite, IRWrite1, IRWrite2,  MUXR1,
+			RegDST, MemToReg, RegWrite, AluSrc2, DIWrite, CZNWrite : out std_logic;
+			AluOp : out std_logic_vector(2 downto 0);
+			controlmemData : out std_logic_vector(18 downto 0);
+			nxtline :out std_logic_vector(3 downto 0);
+			cardata : out std_logic_vector(3 downto 0)
+		);
+			
+end Controller;
+
+architecture behave of Controller is
+
+	component ROM1 is
+		port(
+			opcode: in std_logic_vector(3 downto 0);
+			lineNumber: out std_logic_vector(3 downto 0)
+		);
+	end component;
+	
+	component ROM2 is
+		port(
+			opcode: in std_logic_vector(2 downto 0);
+			lineNumber: out std_logic_vector(3 downto 0)
+		);
+	end component;
+	
+	component ControlMemory is
+		generic (K: integer:=19; -- number of bits per word (data size)
+					W: integer:=4 -- number of address bits  (address size)
+				); 
+		port ( 	clk, rst_n : std_logic;
+					ADDR: in std_logic_vector (W-1 downto 0); -- RAM address
+					DOUT: out std_logic_vector (K-1 downto 0)
+				); -- read data
+	end component;
+	
+	component CAR is
+		port( clk, rst_n : in std_logic;
+			memIndex_input : in std_logic_vector(3 downto 0);
+			memIndex_output : out std_logic_vector(3 downto 0)
+			);
+	end component;
+	
+	component mux_2bits is
+			Generic(W : integer :=4);
+			Port (D0, D1, D2, D3 : in std_logic_vector(W-1 downto 0);
+          S      : in std_logic_vector(1 downto 0);
+          Y      : out std_logic_vector(W-1 downto 0));
+	end component;
+	
+	signal rom1ToMux : std_logic_vector(3 downto 0);
+	signal rom2ToMux : std_logic_vector(3 downto 0);
+	signal nextLine : std_logic_vector(3 downto 0);
+	signal seq : std_logic_vector(1 downto 0) := "00";
+	signal muxOut : std_logic_vector(3 downto 0);
+	signal CARout : std_logic_vector(3 downto 0);
+	signal controlWord : std_logic_vector(18 downto 0) := (others => '0');
+	signal nextlinetemp : std_logic_vector(3 downto 0);
+	signal zero4Signal : std_logic_vector(3 downto 0);
+	
+	
+begin
+	R1: ROM1 port map(opcode, rom1ToMux);
+	R2: ROM2 port map(opcode(3 downto 1), rom2ToMux);
+	
+	zero4signal <= "0000";
+	M: mux_2bits port map(zero4signal, rom1ToMux, rom2ToMux, nextLine, seq, muxOut);
+	
+	C: CAR port map(clk, reset, muxOut, CARout);
+	cardata <= carout;
+	
+	Mem: ControlMemory port map(clk, reset, CARout, controlWord);
+	
+	seq <= controlWord(1 downto 0);
+	nextlinetemp <= CARout + "0001";
+	nextLine <= nextlinetemp;
+	nxtline <= nextline;
+	controlmemData <= controlword;
+	
+	process (clk, reset, controlword) begin
+		if(reset = '0') then
+			pcsrc <= '0';
+			pcwrite <= '0';
+			pcwritecond <= '0';
+			iord <= '0';
+			memwrite <= '0';
+			irwrite1 <= '0';
+			irwrite2 <= '0';
+			muxr1 <= '0';
+			regdst <= '0';
+			memtoreg <= '0';
+			regwrite <= '0';
+			alusrc2 <= '0';
+			aluop <= "000";
+			diwrite <= '0';
+			cznwrite <= '0';
+		else
+				pcsrc <= controlWord(18);
+				pcwrite <= controlWord(17);
+				pcwritecond <= controlWord(16);
+				iord <= controlWord(15);
+				memwrite <= controlWord(14);
+				irwrite1 <= controlWord(13);
+				irwrite2 <= controlWord(12);
+				muxr1 <= controlWord(11);
+				regdst <= controlWord(10);
+				memtoreg <= controlWord(9);
+				regwrite <= controlWord(8);
+				alusrc2 <= controlWord(7);
+				aluop <= controlWord(6 downto 4);
+				diwrite <= controlWord(3);
+				cznwrite <= controlWord(2);
+		end if;
+	end process;
+	
+
+end behave;
+

DI.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    17:03:20 06/25/2017 
+-- Design Name: 
+-- Module Name:    DI - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity DI is
+	port( clk : in std_logic;
+			rst_n : in std_logic;
+			writeDI : in std_logic;
+			Din : in std_logic_vector(4 downto 0);
+			Dout : out std_logic_vector(4 downto 0)
+		);
+end DI;
+
+architecture behave of DI is
+
+begin
+	process (clk, rst_n)
+	begin
+		if rst_n = '0' then
+			Dout <= (others => '0');
+		elsif rising_edge(clk) then
+			if(writeDI = '1') then
+				Dout <= Din;
+			end if;
+		end if;
+	end process;
+
+end behave;
+