Added Template Info

Author: aklsh

.hdl_checker/cache.json

@@ -1,5 +1,23 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: FA.v
+// Modified: 2020-07-16
+// Description: 1-Bit Full Adder module
+//              - Uses primitives for sum and carry outputs
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 primitive carryOut (output Cout, input A, input B, input Cin);
-/*  Truth Table for carry out   */
+
+    // Truth Table for carry out
     table
       // A B Cin    Cout
          1 1  ?   :  1  ;
@@ -12,7 +30,8 @@ primitive carryOut (output Cout, input A, input B, input Cin);
 endprimitive
 
 primitive sumOut (output sum, input A, input B, input Cin);
-/*  Truth Table for sum */
+
+    // Truth Table for sum
     table
       // A B Cin    sum
          1 1  1   :  1  ;
@@ -27,7 +46,8 @@ primitive sumOut (output sum, input A, input B, input Cin);
 endprimitive
 
 module FA(output Cout, output sum, input A, input B, input Cin);
-/*  instantiating sum and carry primitives  */
+
+    // instantiating sum and carry primitives
     sumOut s(sum, A, B, Cin);
     carryOut co(Cout, A, B, Cin);
 endmodule

Adders/FA.v

@@ -1,5 +1,23 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: HA.v
+// Modified: 2020-07-16
+// Description: 1-Bit Half Adder Module
+//
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 primitive outSum(output sum, input A, input B);
-/*  Truth Table for sum */
+
+    // Truth Table for sum
     table
       // A B   sum
          0 0 :  0  ;
@@ -10,7 +28,8 @@ primitive outSum(output sum, input A, input B);
 endprimitive
 
 primitive outCarry(output carry, input A, input B);
-/*  Truth Table for carry out   */
+
+    // Truth Table for carry out
     table
       // A B  carry
          0 0 :  0  ;
@@ -21,7 +40,8 @@ primitive outCarry(output carry, input A, input B);
 endprimitive
 
 module HA (output carry, output sum, input A, input B);
-/*  instantiating sum and carry primitives  */
+
+    // instantiating sum and carry primitives
     outSum s(sum, A, B);
     outCarry c(carry, A, B);
 endmodule

Adders/HA.v

@@ -1,23 +1,42 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: nBitCarryLookAheadAdder.v
+// Modified: 2020-07-16
+// Description: N-Bit Carry Look Ahead Adder
+//
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 module nBitCarryLookAheadAdder #(parameter n = 4)(output[n:0] total, input[n-1:0] A, input[n-1:0] B);
+
     wire[n-1:0] gi, pi, sum;
     wire[n:0] ci;
 
     assign ci[0] = 1'b0;
+
     genvar i;
     generate
-        for(i = 0;i < n;i = i+1)
-            begin: giAndpi
-                assign gi[i] = A[i]&B[i];
-                assign pi[i] = A[i]^B[i];
-                assign ci[i+1] = gi[i]|(pi[i]&ci[i]);
-            end
+        for(i = 0;i < n;i = i+1) begin: giAndpi
+            assign gi[i] = A[i]&B[i];
+            assign pi[i] = A[i]^B[i];
+            assign ci[i+1] = gi[i]|(pi[i]&ci[i]);
+        end
     endgenerate
+
     genvar j;
     generate
-        for(j = 0;j < n;j = j+1)
-            begin: calculation
-                FA adder(.Cout(), .sum(sum[j]), .A(A[j]), .B(B[j]), .Cin(ci[j]));
-            end
+        for(j = 0;j < n;j = j+1) begin: calculation
+            FA adder(.Cout(), .sum(sum[j]), .A(A[j]), .B(B[j]), .Cin(ci[j]));
+        end
     endgenerate
+
     assign total = {ci[n], sum[n-1:0]};
 endmodule

Adders/nBitCarryLookAheadAdder.v

@@ -1,14 +1,33 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: nBitRippleCarryAdder.v
+// Modified: 2020-07-16
+// Description: N-Bit Ripple Carry Adder
+//
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 module nBitRippleCarryAdder #(parameter n = 4)(output[n:0] total, input[n-1:0] A, input[n-1:0] B);
+
     wire[n-1:0] carryMiddle, sum;
+
     genvar i;
     generate
-        for(i = 0;i < n;i = i+1)
-            begin: genAdder
-                if(i == 0)
-                    HA f(carryMiddle[0], sum[0], A[0], B[0]);
-                else
-                    FA f(carryMiddle[i], sum[i], A[i], B[i], carryMiddle[i-1]);
-            end
-        assign total = {carryMiddle[n-1], sum[n-1:0]};
+        for(i = 0;i < n;i = i+1) begin: genAdder
+            if(i == 0)
+                HA f(carryMiddle[0], sum[0], A[0], B[0]);
+            else
+                FA f(carryMiddle[i], sum[i], A[i], B[i], carryMiddle[i-1]);
+        end
     endgenerate
+
+    assign total = {carryMiddle[n-1], sum[n-1:0]};
 endmodule

Adders/nBitRippleCarryAdder.v

@@ -1,16 +1,37 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: nBitCounter.v
+// Modified: 2020-07-16
+// Description: N-Bit Counter, with customisable increment
+//
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 module nBitCounter #(parameter n = 32, parameter inc = 1, parameter seed = 0) (output reg[n-1:0] count, input clk, input rst, input[n-1:0] pl, input load);
-/*  initially set count to start/seed   */
+
+    // initially set count to start/seed
     initial begin
         count = seed;
     end
+
     always @ (posedge clk, rst, load) begin
-    /*  if load input is active, stop counting and take in the load */
+        // if load input is active, stop counting and take in the load
         if(load)
             count = pl;
-    /*  if reset is active, reset to 0  */
+
+        // if reset is active, reset to 0
         else if(rst)
             count = 0;
-    /*  else, increment count by increment value  */
+
+        // else, increment count by increment value
         else
             count = count + inc;
     end

Counters/nBitCounter.v

@@ -1,9 +1,28 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: nBitJohnsonCounter.v
+// Modified: 2020-07-16
+// Description: N-Bit Johnson Counter
+//
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 module nBitJohnsonCounter #(parameter integer n = 8) (output reg[n-1:0] JC, input clk);
-/*  initially feed in 1 to register */
+
+    //  initially feed in 1 to register
     initial begin
         JC = 1;
     end
-/*  every clock edge, shift the bit to right nd connect inverted o/p of last to i/p of first    */
+
+    // every clock edge, shift the bit to right nd connect inverted o/p of last to i/p of first
     always @(posedge clk) begin
         JC = {~JC[0], JC[n-1:1]};
     end

Counters/nBitJohnsonCounter.v

@@ -1,5 +1,22 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: DFF.v
+// Modified: 2020-07-16
+// Description: D-Flip Flop
+//              - No Clear
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 module DFF(output reg Q, input D, input clk);
-/*  DFF is positive edge-triggered  */
+    // DFF is positive edge-triggered
     always@(posedge clk) begin
         Q <= D;
     end

FFs/DFF/DFF.v

@@ -1,7 +1,25 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: DFF_AsyncClear.v
+// Modified: 2020-07-16
+// Description: D-Flip Flop
+//              - Asynchronous Clear
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 module DFF_AsyncClear(output reg Q, input D, input clk, input clr);
-/*  DFF is positive edge-triggered  */
+
+    // DFF is positive edge-triggered
     always @ (posedge clk, clr) begin
-    /*  if clr becomes 1, immediately clear FF o/p to 0*/
+        // if clr becomes 1, immediately clear FF o/p to 0
         if(clr)
             Q <= 1'b0;
         else

FFs/DFF/DFF_AsyncClear.v

@@ -1,7 +1,25 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: DFF_SyncClear.v
+// Modified: 2020-07-16
+// Description: D-Flip Flop
+//              - Synchronous Clear
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 module DFF_SyncClear(output reg Q, input D, input clk, input clr);
-/*  DFF is positive edge-triggered  */
+
+    // DFF is positive edge-triggered
     always @ (posedge clk) begin
-    /*  check if clr is 1, ONLY AT POSITIVE CLOCK EDGE, then clear o/p    */
+        // check if clr is 1, ONLY AT POSITIVE CLOCK EDGE, then clear o/p
         if(clr)
             Q = 1'b0;
         else

FFs/DFF/DFF_SyncClear.v

@@ -1,7 +1,26 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: JKFF.v
+// Modified: 2020-07-16
+// Description: J-K Flip Flop
+//              - No clear
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 module JKFF (output reg Q, input J, input K, input clk);
+
     initial begin
         Q = 0;
     end
+
     always @ (posedge clk) begin
         case({J,K})
             2'b00: Q <= Q;

FFs/JKFF/JKFF.v

@@ -1,7 +1,26 @@
+////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Akilesh Kannan <[email protected]>
+//
+// File: JKFF_AsyncClear.v
+// Modified: 2020-07-16
+// Description: J-K Flip Flop
+//              - Asynchronous clear
+//
+// License: MIT
+//
+////////////////////////////////////////////////////////////////////////
+
+`default_nettype None
+
+`timescale 1ns/1ps
+
 module JKFF_AsyncClear (output reg Q, input J, input K, input clr, input clk);
+
     initial begin
         Q = 0;
     end
+
     always @ (posedge clk, posedge clr) begin
         if(clr)
             Q <= 0;