Wrong output with to_json and to_blif command

[Anne-Me]

I am trying to generate a circuit from a verilog file using the following yosys script

read_verilog topEntity.v
hierarchy -check -top topEntity
synth
write_blif out.blif

topEntity.txt

(The topEntity.v file was generated by Clash, it implements the shift rows step of an AES encryption.)

I am trying to create a circuit file using the to_blif or to_json command but it seems like some errors are introduced there. When simulating the out.blif or out.json files they give the wrong results.
I also tried write_verilog out.v and simulated out.v using iverilog and the result is correct, so it seems like the synth command is not introducing any issues.

Since I am simulating the blif and json circuits with my own code there could be an error in the interpretation of the formats on my side but looking at the out files themselves I can already see mistakes. For example here is an excerpt from the json output:

  "creator": "Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90, g++ 11.4.0-1ubuntu1~22.04 -fPIC -O3)",
  "modules": {
    "topEntity": {
      "attributes": {
        "top": "00000000000000000000000000000001",
        "src": "verilog/Example.Project.topEntity/topEntity.v:5.1-213.10"
      },
      "ports": {
        "x_0": {
          "direction": "input",
          "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 ]
        },
        "x_1": {
          "direction": "input",
          "bits": [ 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65 ]
        },
        "x_2": {
          "direction": "input",
          "bits": [ 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97 ]
        },
        "x_3": {
          "direction": "input",
          "bits": [ 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129 ]
        },
        "result_0": {
          "direction": "output",
          "bits": [ 98, 99, 100, 101, 102, 103, 104, 105, 74, 75, 76, 77, 78, 79, 80, 81, 50, 51, 52, 53, 54, 55, 56, 57, 26, 27, 28, 29, 30, 31, 32, 33 ]
        },
        "result_1": {
          "direction": "output",
          "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 106, 107, 108, 109, 110, 111, 112, 113, 82, 83, 84, 85, 86, 87, 88, 89, 58, 59, 60, 61, 62, 63, 64, 65 ]
        },
        "result_2": {
          "direction": "output",
          "bits": [ 34, 35, 36, 37, 38, 39, 40, 41, 10, 11, 12, 13, 14, 15, 16, 17, 114, 115, 116, 117, 118, 119, 120, 121, 90, 91, 92, 93, 94, 95, 96, 97 ]
        },
        "result_3": {
          "direction": "output",
          "bits": [ 66, 67, 68, 69, 70, 71, 72, 73, 42, 43, 44, 45, 46, 47, 48, 49, 18, 19, 20, 21, 22, 23, 24, 25, 122, 123, 124, 125, 126, 127, 128, 129 ]
        }
      },
      "cells": {
      },

The first 8 bits of the first input are not supposed to move, therefore

"result_0": {
"direction": "output",
"bits": [ 98, 99, 100, 101, 102, 103, 104, 105, ...

is wrong it should be

"result_0": {
"direction": "output",
"bits": [ 2, 3, 4, 5, 6, 7, 8, 9, ...

[KrystalDelusion]

Uhh, I'm not very familiar with the json output but AFAIK it is often used with nextpnr so if it was wrong it would be obvious pretty quickly. Taking a look at your example and comparing the RTLIL with the json we get

connect \result_0 { \x_0 [31:24] \x_1 [23:16] \x_2 [15:8] \x_3 [7:0] }

"x_0": {
  "direction": "input",
  "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 ]
},
..
"x_3": {
  "direction": "input",
  "bits": [ 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129 ]
},
..
"result_0": {
  "direction": "output",
  "bits": [ 98, 99, 100, 101, 102, 103, 104, 105, 74, 75, 76, 77, 78, 79, 80, 81, 50, 51, 52, 53, 54, 55, 56, 57, 26, 27, 28, 29, 30, 31, 32, 33 ]
},

The result_0 includes bits 26, 27, 28, 29, 30, 31, 32, 33 from x_0 (the 8 most significant bits, x_0[31:24]) and bits 98, 99, 100, 101, 102, 103, 104, 105 from x_3 (the 8 least significant bits, x_3[7:0]). Are you by chance trying to read them as most significant bit first instead?

[Anne-Me]

thanks for checking, this is still a bit confusing since I was operating on the bit level in my original program. So it is surprising that the order would get changed. The RTLIL expression is from before running the to_json command? I will have to run some more tests.