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SamuelHo10SamuelHo10
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renamed pairs and replaced .first and .second with ={} notation
1 parent 700cc75 commit d0c4cb9

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6 files changed

+28
-39
lines changed

6 files changed

+28
-39
lines changed

‎libs/libarchfpga/src/arch_util.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -533,7 +533,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
533533
copy->annotations[i].line_num = pb_type->annotations[i].line_num;
534534
copy->annotations[i].format = pb_type->annotations[i].format;
535535
copy->annotations[i].type = pb_type->annotations[i].type;
536-
copy->annotations[i].pairs = pb_type->annotations[i].pairs;
536+
copy->annotations[i].annotation_entries = pb_type->annotations[i].annotation_entries;
537537
}
538538
}
539539

@@ -604,7 +604,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
604604
lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format;
605605
lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type;
606606

607-
lut_pb_type->modes[0].interconnect[0].annotations[i].pairs = lut_pb_type->annotations[i].pairs;
607+
lut_pb_type->modes[0].interconnect[0].annotations[i].annotation_entries = lut_pb_type->annotations[i].annotation_entries;
608608
}
609609

610610
/* Second mode, LUT */
@@ -1070,7 +1070,7 @@ const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_ty
10701070
const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot];
10711071
InstPort annot_in(annot->input_pins);
10721072
if (annot_in.port_name() == port->name) {
1073-
for (const auto& [key, val] : annot->pairs) {
1073+
for (const auto& [key, val] : annot->annotation_entries) {
10741074
if (key == annot_type) {
10751075
return annot;
10761076
}
@@ -1089,7 +1089,7 @@ const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb
10891089
for (const auto& annot_out_str : vtr::split(annot->output_pins)) {
10901090
InstPort out_pins(annot_out_str);
10911091
if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
1092-
for (const auto& [key, val] : annot->pairs) {
1092+
for (const auto& [key, val] : annot->annotation_entries) {
10931093
if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX
10941094
|| key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
10951095
return annot;

‎libs/libarchfpga/src/echo_arch.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -413,7 +413,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
413413
pb_type->modes[i].interconnect[j].annotations[k].input_pins,
414414
pb_type->modes[i].interconnect[j].annotations[k].output_pins,
415415
pb_type->modes[i].interconnect[j].annotations[k].format,
416-
pb_type->modes[i].interconnect[j].annotations[k].pairs[0].second.c_str());
416+
pb_type->modes[i].interconnect[j].annotations[k].annotation_entries[0].second.c_str());
417417
}
418418
//Print power info for interconnects
419419
if (pb_type->modes[i].interconnect[j].interconnect_power) {
@@ -441,7 +441,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
441441
pb_type->annotations[k].input_pins,
442442
pb_type->annotations[k].output_pins,
443443
pb_type->annotations[k].format,
444-
pb_type->annotations[k].pairs[0].second.c_str());
444+
pb_type->annotations[k].annotation_entries[0].second.c_str());
445445
}
446446
}
447447
}

‎libs/libarchfpga/src/physical_types.h

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1312,8 +1312,7 @@ struct t_mode_power {
13121312
* This is later for additional information.
13131313
*
13141314
* Data Members:
1315-
* value: value/property pair
1316-
* prop: value/property pair
1315+
* annotation_entries: pairs of annotation subtypes and the annotation values
13171316
* type: type of annotation
13181317
* format: formatting of data
13191318
* input_pins: input pins as string affected by annotation
@@ -1322,7 +1321,7 @@ struct t_mode_power {
13221321
*/
13231322
struct t_pin_to_pin_annotation {
13241323

1325-
std::vector<std::pair<int, std::string>> pairs;
1324+
std::vector<std::pair<int, std::string>> annotation_entries;
13261325

13271326
enum e_pin_to_pin_annotation_type type;
13281327
enum e_pin_to_pin_annotation_format format;
@@ -1334,7 +1333,7 @@ struct t_pin_to_pin_annotation {
13341333
int line_num; /* used to report what line number this annotation is found in architecture file */
13351334

13361335
t_pin_to_pin_annotation() {
1337-
pairs = std::vector<std::pair<int, std::string>>();
1336+
annotation_entries = std::vector<std::pair<int, std::string>>();
13381337
input_pins = nullptr;
13391338
output_pins = nullptr;
13401339
clock = nullptr;

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string
245245

246246
pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
247247
pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT;
248-
pp.pairs.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name});
248+
pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name});
249249
pp.input_pins = vtr::strdup(input.c_str());
250250
pp.output_pins = vtr::strdup(output.c_str());
251251

‎libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 14 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -882,7 +882,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
882882
i = 1;
883883
}
884884

885-
annotation->pairs.resize(i);
885+
annotation->annotation_entries.resize(i);
886886
annotation->line_num = loc_data.line(Parent);
887887
/* Todo: This is slow, I should use a case lookup */
888888
i = 0;
@@ -891,14 +891,12 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
891891
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
892892
Prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
893893
if (Prop) {
894-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX;
895-
annotation->pairs[i].second = Prop;
894+
annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MAX, Prop};
896895
i++;
897896
}
898897
Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
899898
if (Prop) {
900-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN;
901-
annotation->pairs[i].second = Prop;
899+
annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MIN, Prop};
902900
i++;
903901
}
904902
Prop = get_attribute(Parent, "in_port", loc_data).value();
@@ -911,13 +909,13 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
911909
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
912910
annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX;
913911
Prop = get_attribute(Parent, "type", loc_data).value();
914-
annotation->pairs[i].second = Parent.child_value();
912+
annotation->annotation_entries[i].second = Parent.child_value();
915913

916914
if (0 == strcmp(Prop, "max")) {
917-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX;
915+
annotation->annotation_entries[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX;
918916
} else {
919917
VTR_ASSERT(0 == strcmp(Prop, "min"));
920-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN;
918+
annotation->annotation_entries[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN;
921919
}
922920

923921
i++;
@@ -931,8 +929,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
931929
annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE;
932930
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
933931
Prop = get_attribute(Parent, "C", loc_data).value();
934-
annotation->pairs[i].second = Prop;
935-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_CAPACITANCE_C;
932+
annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_CAPACITANCE_C, Prop};
936933
i++;
937934

938935
Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
@@ -945,8 +942,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
945942
} else if (0 == strcmp(Parent.name(), "C_matrix")) {
946943
annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE;
947944
annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX;
948-
annotation->pairs[i].second = Parent.child_value();
949-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_CAPACITANCE_C;
945+
annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_CAPACITANCE_C, Parent.child_value()};
950946
i++;
951947

952948
Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
@@ -960,9 +956,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
960956
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
961957
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
962958
Prop = get_attribute(Parent, "value", loc_data).value();
963-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_TSETUP;
964-
annotation->pairs[i].second = Prop;
965-
959+
annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_TSETUP, Prop};
966960
i++;
967961
Prop = get_attribute(Parent, "port", loc_data).value();
968962
annotation->input_pins = vtr::strdup(Prop);
@@ -979,15 +973,13 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
979973

980974
bool found_min_max_attrib = false;
981975
if (Prop) {
982-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX;
983-
annotation->pairs[i].second = Prop;
976+
annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX, Prop};
984977
i++;
985978
found_min_max_attrib = true;
986979
}
987980
Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
988981
if (Prop) {
989-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN;
990-
annotation->pairs[i].second = Prop;
982+
annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN, Prop};
991983
i++;
992984
found_min_max_attrib = true;
993985
}
@@ -1010,8 +1002,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
10101002
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
10111003
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
10121004
Prop = get_attribute(Parent, "value", loc_data).value();
1013-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_THOLD;
1014-
annotation->pairs[i].second = Prop;
1005+
annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_THOLD, Prop};
10151006
i++;
10161007

10171008
Prop = get_attribute(Parent, "port", loc_data).value();
@@ -1026,8 +1017,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
10261017
annotation->type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
10271018
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
10281019
Prop = get_attribute(Parent, "name", loc_data).value();
1029-
annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME;
1030-
annotation->pairs[i].second = Prop;
1020+
annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, Prop};
10311021
i++;
10321022

10331023
Prop = get_attribute(Parent, "in_port", loc_data).value();
@@ -1041,7 +1031,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
10411031
"Unknown port type %s in %s in %s", Parent.name(),
10421032
Parent.parent().name(), Parent.parent().parent().name());
10431033
}
1044-
VTR_ASSERT(i == static_cast<int>(annotation->pairs.size()));
1034+
VTR_ASSERT(i == static_cast<int>(annotation->annotation_entries.size()));
10451035
}
10461036

10471037
static void ProcessPb_TypePowerPinToggle(pugi::xml_node parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) {

‎vpr/src/pack/pb_type_graph_annotations.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) {
5151
annotations = pb_type->annotations;
5252
for (i = 0; i < pb_type->num_annotations; i++) {
5353
if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) {
54-
for (const auto& [key, val] : annotations[i].pairs) {
54+
for (const auto& [key, val] : annotations[i].annotation_entries) {
5555
if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX
5656
|| key == E_ANNOT_PIN_TO_PIN_DELAY_MIN
5757
|| key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX
@@ -77,7 +77,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) {
7777
annotations = pb_type->modes[i].interconnect[j].annotations;
7878
for (k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; k++) {
7979
if (annotations[k].type == E_ANNOT_PIN_TO_PIN_DELAY) {
80-
for (const auto& [key, val] : annotations[k].pairs) {
80+
for (const auto& [key, val] : annotations[k].annotation_entries) {
8181
if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX
8282
|| key == E_ANNOT_PIN_TO_PIN_DELAY_MIN
8383
|| key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX
@@ -96,11 +96,11 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) {
9696
}
9797
}
9898
} else if (annotations[k].type == E_ANNOT_PIN_TO_PIN_PACK_PATTERN) {
99-
VTR_ASSERT(annotations[k].pairs.size() == 1);
99+
VTR_ASSERT(annotations[k].annotation_entries.size() == 1);
100100
load_pack_pattern_annotations(annotations[k].line_num, pb_graph_node, i,
101101
annotations[k].input_pins,
102102
annotations[k].output_pins,
103-
annotations[k].pairs[0].second);
103+
annotations[k].annotation_entries[0].second);
104104
} else {
105105
/* Todo:
106106
* load_power_annotations(pb_graph_node);

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