What is the cycle latency of VexRiscv FPU double‑precision add (FADD.D), and how can I derive it from the RTL/config?

[Usutatsu]

Docs say the FPU is deeply pipelined (e.g., ~10 stages for FMA) and can issue 1 op/cycle except FDIV/FSQRT/subnormals, but I can’t find the latency for FADD.D. Is there a canonical number or a config‑dependent answer? If it’s the latter, what’s the recommended way to read the add pipeline depth from FpuCore.scala? Any pointer would help. Thanks!

[Dolu1990]

Hi,

Would need to count the number of registers between the RF read and RF write on https://github.com/SpinalHDL/VexiiRiscv/blob/dev/src/main/scala/vexiiriscv/soc/litex/Soc.scala#L533

I count 9 stage for FADD, probably FMA seems to be more like 13. But would need to do a mesurment, as the diagram may not be exact

way to read the add pipeline

Don't read, it is too easy to do a mistake ^^
Best way is to run a simulation and mesure.