Multi cycle paths instead of pipelines

[JulianKemmerer]

Add an option to render comb logic with multi cycle path constraints between in and out reg, instead of adding pipelining regs.

[chili-chips-ba]

The proposal is to provide an option for PipelineC insert to insert only input and final output pipe stages, leaving everything in-between as combo. And, based on the timing reports, have it insert delayed RDY/VLD handshake with surrounding blocks, also generating SDC for MCP between those input and output flops.

By doing this we can:

1. save big on the pipeline flops
2. save some on the latency (which is directly related to throughput in some cases, such as Poly1305)

The 2nd saving comes from the fact that pipeline stages cannot be inserted at the exact point where needed. They also cannot be fully balanced. Every pipeline stage will typically leave 10% to 30% timing margin. This timing margin is additive -- It accumulates along the pipeline.

We can recover it by not breaking up the combo logic into pipelines. In other words, for the 10% overhead, we may instead of 10 pipelines have one large combo with MCP=9, i.e. save not only a ton of flops, but also one clock cycle.

That said, do we have a measure for the typical timing overhead of auto-inserted pipelines?
Is it possible to dial-it in, such as by saying:

• Insert a pipeline stage at the point where a given percentage (e.g. 85%) of the clock budget is consumed.

We could even take it further and say:

• Insert a pipeline stage assuming the timing budget is a given number of clock cycles (which is a precursor to MCP)