@@ -114,20 +114,9 @@ void Tle94112::_configHB(uint8_t hb, uint8_t state, uint8_t pwm, uint8_t activeF
114114
115115 TLE94112_LOG_MSG (__FUNCTION__);
116116
117- uint8_t reg = mHalfBridges [hb].stateReg ;
118- uint8_t mask = mHalfBridges [hb].stateMask ;
119- uint8_t shift = mHalfBridges [hb].stateShift ;
120- writeReg (reg, mask, shift, state);
121-
122- reg = mHalfBridges [hb].pwmReg ;
123- mask = mHalfBridges [hb].pwmMask ;
124- shift = mHalfBridges [hb].pwmShift ;
125- writeReg (reg, mask, shift, pwm);
126-
127- reg = mHalfBridges [hb].fwReg ;
128- mask = mHalfBridges [hb].fwMask ;
129- shift = mHalfBridges [hb].fwShift ;
130- writeReg (reg, mask, shift, activeFW);
117+ writeReg (mHalfBridges [hb].stateReg , mHalfBridges [hb].stateMask , mHalfBridges [hb].stateShift , state);
118+ writeReg (mHalfBridges [hb].pwmReg , mHalfBridges [hb].pwmMask , mHalfBridges [hb].pwmShift , pwm);
119+ writeReg (mHalfBridges [hb].fwReg , mHalfBridges [hb].fwMask , mHalfBridges [hb].fwShift , activeFW);
131120}
132121
133122void Tle94112::configPWM (PWMChannel pwm, PWMFreq freq, uint8_t dutyCycle)
@@ -140,15 +129,8 @@ void Tle94112::_configPWM(uint8_t pwm, uint8_t freq, uint8_t dutyCycle)
140129
141130 TLE94112_LOG_MSG (__FUNCTION__);
142131
143- uint8_t reg = mPwmChannels [pwm].freqReg ;
144- uint8_t mask = mPwmChannels [pwm].freqMask ;
145- uint8_t shift = mPwmChannels [pwm].freqShift ;
146- writeReg (reg, mask, shift, freq);
147-
148- reg = mPwmChannels [pwm].dcReg ;
149- mask = mPwmChannels [pwm].dcMask ;
150- shift = mPwmChannels [pwm].dcShift ;
151- writeReg (reg, mask, shift, dutyCycle);
132+ writeReg (mPwmChannels [pwm].freqReg , mPwmChannels [pwm].freqMask , mPwmChannels [pwm].freqShift , freq);
133+ writeReg (mPwmChannels [pwm].dcReg , mPwmChannels [pwm].dcMask , mPwmChannels [pwm].dcShift , dutyCycle);
152134}
153135
154136uint8_t Tle94112::setLedMode (HalfBridge hb, uint8_t active)
@@ -196,10 +178,7 @@ uint8_t Tle94112::_getHBOverCurrent(uint8_t hb)
196178{
197179 TLE94112_LOG_MSG (__FUNCTION__);
198180
199- uint8_t reg = mHalfBridges [hb].ocReg ;
200- uint8_t mask = mHalfBridges [hb].ocMask ;
201- uint8_t shift = mHalfBridges [hb].ocShift ;
202- return readStatusReg (reg, mask, shift);
181+ return readStatusReg (mHalfBridges [hb].ocReg , mHalfBridges [hb].ocMask , mHalfBridges [hb].ocShift );
203182}
204183
205184uint8_t Tle94112::getHBOpenLoad (HalfBridge hb)
@@ -211,10 +190,7 @@ uint8_t Tle94112::_getHBOpenLoad(uint8_t hb)
211190{
212191 TLE94112_LOG_MSG (__FUNCTION__);
213192
214- uint8_t reg = mHalfBridges [hb].olReg ;
215- uint8_t mask = mHalfBridges [hb].olMask ;
216- uint8_t shift = mHalfBridges [hb].olShift ;
217- return readStatusReg (reg, mask, shift);
193+ return readStatusReg (mHalfBridges [hb].olReg , mHalfBridges [hb].olMask , mHalfBridges [hb].olShift );
218194}
219195
220196void Tle94112::clearErrors ()
@@ -235,39 +211,39 @@ void Tle94112::init(void)
235211 TLE94112_LOG_MSG (__FUNCTION__);
236212
237213 // !< initial control register configuration
238- mCtrlRegAddresses [static_cast <int >(Tle94112::HB_ACT_1_CTRL)] = 0x03 ;
214+ mCtrlRegAddresses [HB_ACT_1_CTRL] = REG_ACT_1;
215+ mCtrlRegAddresses [HB_ACT_2_CTRL] = REG_ACT_2;
216+ mCtrlRegAddresses [HB_ACT_3_CTRL] = REG_ACT_3;
217+ mCtrlRegAddresses [HB_MODE_1_CTRL] = REG_MODE_1;
218+ mCtrlRegAddresses [HB_MODE_2_CTRL] = REG_MODE_2;
219+ mCtrlRegAddresses [HB_MODE_3_CTRL] = REG_MODE_3;
220+ mCtrlRegAddresses [PWM_CH_FREQ_CTRL] = REG_PWM_CH_FREQ;
221+ mCtrlRegAddresses [PWM1_DC_CTRL] = REG_PWM_DC_1;
222+ mCtrlRegAddresses [PWM2_DC_CTRL] = REG_PWM_DC_2;
223+ mCtrlRegAddresses [PWM3_DC_CTRL] = REG_PWM_DC_3;
224+ mCtrlRegAddresses [FW_OL_CTRL] = REG_FW_OL;
225+ mCtrlRegAddresses [FW_CTRL] = REG_FW_CTRL;
239226 mCtrlRegData [HB_ACT_1_CTRL] = 0 ;
240- mCtrlRegAddresses [HB_ACT_2_CTRL] = 0x43 ;
241227 mCtrlRegData [HB_ACT_2_CTRL] = 0 ;
242- mCtrlRegAddresses [HB_ACT_3_CTRL] = 0x23 ;
243228 mCtrlRegData [HB_ACT_3_CTRL] = 0 ;
244- mCtrlRegAddresses [HB_MODE_1_CTRL] = 0x63 ;
245229 mCtrlRegData [HB_MODE_1_CTRL] = 0 ;
246- mCtrlRegAddresses [HB_MODE_2_CTRL] = 0x13 ;
247230 mCtrlRegData [HB_MODE_2_CTRL] = 0 ;
248- mCtrlRegAddresses [HB_MODE_3_CTRL] = 0x53 ;
249231 mCtrlRegData [HB_MODE_3_CTRL] = 0 ;
250- mCtrlRegAddresses [PWM_CH_FREQ_CTRL] = 0x33 ;
251232 mCtrlRegData [PWM_CH_FREQ_CTRL] = 0 ;
252- mCtrlRegAddresses [PWM1_DC_CTRL] = 0x73 ;
253233 mCtrlRegData [PWM1_DC_CTRL] = 0 ;
254- mCtrlRegAddresses [PWM2_DC_CTRL] = 0x0B ;
255234 mCtrlRegData [PWM2_DC_CTRL] = 0 ;
256- mCtrlRegAddresses [PWM3_DC_CTRL] = 0x4B ;
257235 mCtrlRegData [PWM3_DC_CTRL] = 0 ;
258- mCtrlRegAddresses [FW_OL_CTRL] = 0x2B ;
259236 mCtrlRegData [FW_OL_CTRL] = 0 ;
260- mCtrlRegAddresses [FW_CTRL] = 0x6B ;
261237 mCtrlRegData [FW_CTRL] = 0 ;
262238
263239 // !< status register configuration
264- mStatusRegAddresses [SYS_DIAG1] = 0x1B ;
265- mStatusRegAddresses [OP_ERROR_1_STAT] = 0x5B ;
266- mStatusRegAddresses [OP_ERROR_2_STAT] = 0x3B ;
267- mStatusRegAddresses [OP_ERROR_3_STAT] = 0x7B ;
268- mStatusRegAddresses [OP_ERROR_4_STAT] = 0x07 ;
269- mStatusRegAddresses [OP_ERROR_5_STAT] = 0x47 ;
270- mStatusRegAddresses [OP_ERROR_6_STAT] = 0x27 ;
240+ mStatusRegAddresses [SYS_DIAG1] = REG_SYS_DIAG ;
241+ mStatusRegAddresses [OP_ERROR_1_STAT] = REG_ERR1 ;
242+ mStatusRegAddresses [OP_ERROR_2_STAT] = REG_ERR2 ;
243+ mStatusRegAddresses [OP_ERROR_3_STAT] = REG_ERR3 ;
244+ mStatusRegAddresses [OP_ERROR_4_STAT] = REG_ERR4 ;
245+ mStatusRegAddresses [OP_ERROR_5_STAT] = REG_ERR5 ;
246+ mStatusRegAddresses [OP_ERROR_6_STAT] = REG_ERR6 ;
271247
272248 // !< bit masking for all halfbridges
273249 mHalfBridges [TLE_NOHB] = { HB_ACT_1_CTRL, 0x00 , 0 , HB_MODE_1_CTRL, 0x00 , 0 , FW_OL_CTRL, 0x00 , 0 , OP_ERROR_1_STAT, 0x00 , 0 , OP_ERROR_4_STAT, 0x00 , 0 };
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