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using namespace tle94112 ;
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+ /* ! \brief SPI address commands */
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+ #define TLE94112_CMD_WRITE 0x80 ;
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+ #define TLE94112_CMD_CLEAR 0x80 ;
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+
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#define TLE94112_STATUS_INV_MASK (Tle94112::TLE_POWER_ON_RESET)
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+ /* ! \brief time in milliseconds to wait for chipselect signal raised */
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+ #define TLE94112_CS_RISETIME 2
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+
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+ /* ! \brief micro rise time to wait for chipselect signal raised */
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+ #define TLE94112_CS_MICRO_RISETIME 150
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+
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+
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Tle94112::Tle94112 (void )
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{
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sBus = NULL ;
@@ -114,20 +125,9 @@ void Tle94112::_configHB(uint8_t hb, uint8_t state, uint8_t pwm, uint8_t activeF
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TLE94112_LOG_MSG (__FUNCTION__);
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- uint8_t reg = mHalfBridges [hb].stateReg ;
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- uint8_t mask = mHalfBridges [hb].stateMask ;
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- uint8_t shift = mHalfBridges [hb].stateShift ;
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- writeReg (reg, mask, shift, state);
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-
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- reg = mHalfBridges [hb].pwmReg ;
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- mask = mHalfBridges [hb].pwmMask ;
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- shift = mHalfBridges [hb].pwmShift ;
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- writeReg (reg, mask, shift, pwm);
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-
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- reg = mHalfBridges [hb].fwReg ;
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- mask = mHalfBridges [hb].fwMask ;
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- shift = mHalfBridges [hb].fwShift ;
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- writeReg (reg, mask, shift, activeFW);
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+ writeReg (mHalfBridges [hb].stateReg , mHalfBridges [hb].stateMask , mHalfBridges [hb].stateShift , state);
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+ writeReg (mHalfBridges [hb].pwmReg , mHalfBridges [hb].pwmMask , mHalfBridges [hb].pwmShift , pwm);
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+ writeReg (mHalfBridges [hb].fwReg , mHalfBridges [hb].fwMask , mHalfBridges [hb].fwShift , activeFW);
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}
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void Tle94112::configPWM (PWMChannel pwm, PWMFreq freq, uint8_t dutyCycle)
@@ -140,15 +140,8 @@ void Tle94112::_configPWM(uint8_t pwm, uint8_t freq, uint8_t dutyCycle)
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TLE94112_LOG_MSG (__FUNCTION__);
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- uint8_t reg = mPwmChannels [pwm].freqReg ;
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- uint8_t mask = mPwmChannels [pwm].freqMask ;
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- uint8_t shift = mPwmChannels [pwm].freqShift ;
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- writeReg (reg, mask, shift, freq);
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-
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- reg = mPwmChannels [pwm].dcReg ;
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- mask = mPwmChannels [pwm].dcMask ;
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- shift = mPwmChannels [pwm].dcShift ;
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- writeReg (reg, mask, shift, dutyCycle);
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+ writeReg (mPwmChannels [pwm].freqReg , mPwmChannels [pwm].freqMask , mPwmChannels [pwm].freqShift , freq);
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+ writeReg (mPwmChannels [pwm].dcReg , mPwmChannels [pwm].dcMask , mPwmChannels [pwm].dcShift , dutyCycle);
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}
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uint8_t Tle94112::setLedMode (HalfBridge hb, uint8_t active)
@@ -196,10 +189,7 @@ uint8_t Tle94112::_getHBOverCurrent(uint8_t hb)
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{
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TLE94112_LOG_MSG (__FUNCTION__);
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- uint8_t reg = mHalfBridges [hb].ocReg ;
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- uint8_t mask = mHalfBridges [hb].ocMask ;
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- uint8_t shift = mHalfBridges [hb].ocShift ;
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- return readStatusReg (reg, mask, shift);
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+ return readStatusReg (mHalfBridges [hb].ocReg , mHalfBridges [hb].ocMask , mHalfBridges [hb].ocShift );
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}
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uint8_t Tle94112::getHBOpenLoad (HalfBridge hb)
@@ -211,10 +201,7 @@ uint8_t Tle94112::_getHBOpenLoad(uint8_t hb)
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{
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TLE94112_LOG_MSG (__FUNCTION__);
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- uint8_t reg = mHalfBridges [hb].olReg ;
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- uint8_t mask = mHalfBridges [hb].olMask ;
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- uint8_t shift = mHalfBridges [hb].olShift ;
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- return readStatusReg (reg, mask, shift);
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+ return readStatusReg (mHalfBridges [hb].olReg , mHalfBridges [hb].olMask , mHalfBridges [hb].olShift );
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}
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void Tle94112::clearErrors ()
@@ -235,39 +222,39 @@ void Tle94112::init(void)
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TLE94112_LOG_MSG (__FUNCTION__);
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// !< initial control register configuration
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- mCtrlRegAddresses [static_cast <int >(Tle94112::HB_ACT_1_CTRL)] = 0x03 ;
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+ mCtrlRegAddresses [HB_ACT_1_CTRL] = REG_ACT_1;
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+ mCtrlRegAddresses [HB_ACT_2_CTRL] = REG_ACT_2;
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+ mCtrlRegAddresses [HB_ACT_3_CTRL] = REG_ACT_3;
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+ mCtrlRegAddresses [HB_MODE_1_CTRL] = REG_MODE_1;
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+ mCtrlRegAddresses [HB_MODE_2_CTRL] = REG_MODE_2;
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+ mCtrlRegAddresses [HB_MODE_3_CTRL] = REG_MODE_3;
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+ mCtrlRegAddresses [PWM_CH_FREQ_CTRL] = REG_PWM_CH_FREQ;
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+ mCtrlRegAddresses [PWM1_DC_CTRL] = REG_PWM_DC_1;
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+ mCtrlRegAddresses [PWM2_DC_CTRL] = REG_PWM_DC_2;
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+ mCtrlRegAddresses [PWM3_DC_CTRL] = REG_PWM_DC_3;
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+ mCtrlRegAddresses [FW_OL_CTRL] = REG_FW_OL;
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+ mCtrlRegAddresses [FW_CTRL] = REG_FW_CTRL;
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mCtrlRegData [HB_ACT_1_CTRL] = 0 ;
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- mCtrlRegAddresses [HB_ACT_2_CTRL] = 0x43 ;
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mCtrlRegData [HB_ACT_2_CTRL] = 0 ;
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- mCtrlRegAddresses [HB_ACT_3_CTRL] = 0x23 ;
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mCtrlRegData [HB_ACT_3_CTRL] = 0 ;
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- mCtrlRegAddresses [HB_MODE_1_CTRL] = 0x63 ;
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mCtrlRegData [HB_MODE_1_CTRL] = 0 ;
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- mCtrlRegAddresses [HB_MODE_2_CTRL] = 0x13 ;
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mCtrlRegData [HB_MODE_2_CTRL] = 0 ;
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- mCtrlRegAddresses [HB_MODE_3_CTRL] = 0x53 ;
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mCtrlRegData [HB_MODE_3_CTRL] = 0 ;
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- mCtrlRegAddresses [PWM_CH_FREQ_CTRL] = 0x33 ;
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mCtrlRegData [PWM_CH_FREQ_CTRL] = 0 ;
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- mCtrlRegAddresses [PWM1_DC_CTRL] = 0x73 ;
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mCtrlRegData [PWM1_DC_CTRL] = 0 ;
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- mCtrlRegAddresses [PWM2_DC_CTRL] = 0x0B ;
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mCtrlRegData [PWM2_DC_CTRL] = 0 ;
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- mCtrlRegAddresses [PWM3_DC_CTRL] = 0x4B ;
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mCtrlRegData [PWM3_DC_CTRL] = 0 ;
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- mCtrlRegAddresses [FW_OL_CTRL] = 0x2B ;
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mCtrlRegData [FW_OL_CTRL] = 0 ;
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- mCtrlRegAddresses [FW_CTRL] = 0x6B ;
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mCtrlRegData [FW_CTRL] = 0 ;
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// !< status register configuration
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- mStatusRegAddresses [SYS_DIAG1] = 0x1B ;
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- mStatusRegAddresses [OP_ERROR_1_STAT] = 0x5B ;
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- mStatusRegAddresses [OP_ERROR_2_STAT] = 0x3B ;
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- mStatusRegAddresses [OP_ERROR_3_STAT] = 0x7B ;
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- mStatusRegAddresses [OP_ERROR_4_STAT] = 0x07 ;
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- mStatusRegAddresses [OP_ERROR_5_STAT] = 0x47 ;
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- mStatusRegAddresses [OP_ERROR_6_STAT] = 0x27 ;
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+ mStatusRegAddresses [SYS_DIAG1] = REG_SYS_DIAG ;
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+ mStatusRegAddresses [OP_ERROR_1_STAT] = REG_ERR1 ;
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+ mStatusRegAddresses [OP_ERROR_2_STAT] = REG_ERR2 ;
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+ mStatusRegAddresses [OP_ERROR_3_STAT] = REG_ERR3 ;
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+ mStatusRegAddresses [OP_ERROR_4_STAT] = REG_ERR4 ;
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+ mStatusRegAddresses [OP_ERROR_5_STAT] = REG_ERR5 ;
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+ mStatusRegAddresses [OP_ERROR_6_STAT] = REG_ERR6 ;
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// !< bit masking for all halfbridges
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mHalfBridges [TLE_NOHB] = { HB_ACT_1_CTRL, 0x00 , 0 , HB_MODE_1_CTRL, 0x00 , 0 , FW_OL_CTRL, 0x00 , 0 , OP_ERROR_1_STAT, 0x00 , 0 , OP_ERROR_4_STAT, 0x00 , 0 };
@@ -292,14 +279,6 @@ void Tle94112::init(void)
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}
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- /* ! \brief SPI address commands */
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- #define TLE94112_CMD_WRITE 0x80 ;
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- #define TLE94112_CMD_CLEAR 0x80 ;
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-
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- #define TLE94112_STATUS_INV_MASK (Tle94112::TLE_POWER_ON_RESET)
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-
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- /* ! \brief time in milliseconds to wait for chipselect signal raised */
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- #define TLE94112_CS_RISETIME 2
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void Tle94112::directWriteReg (uint8_t reg, uint8_t data)
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{
@@ -313,7 +292,7 @@ void Tle94112::directWriteReg(uint8_t reg, uint8_t data)
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sBus ->transfer (address, byte0);
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sBus ->transfer (data, byte1);
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cs->enable ();
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- timer->delayMilli (TLE94112_CS_RISETIME );
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+ timer->delayMicro (TLE94112_CS_MICRO_RISETIME );
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}
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void Tle94112::writeReg (uint8_t reg, uint8_t mask, uint8_t shift, uint8_t data)
@@ -354,7 +333,7 @@ uint8_t Tle94112::readStatusReg(uint8_t reg, uint8_t mask, uint8_t shift)
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sBus ->transfer (address,byte0);
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sBus ->transfer (0xFF ,received);
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cs->enable ();
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- timer->delayMilli (TLE94112_CS_RISETIME );
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+ timer->delayMicro (TLE94112_CS_MICRO_RISETIME );
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received = (received & mask) >> shift;
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@@ -374,5 +353,5 @@ void Tle94112::clearStatusReg(uint8_t reg)
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sBus ->transfer (address,byte0);
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sBus ->transfer (0 ,byte1);
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cs->enable ();
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- timer->delayMilli (TLE94112_CS_RISETIME );
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+ timer->delayMicro (TLE94112_CS_MICRO_RISETIME );
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}
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