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Merge pull request #6 from Infineon/DESMAKERS-4585
Desmakers 4585
2 parents 18ac483 + 51c0135 commit 4b2883f

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7 files changed

+51
-76
lines changed

7 files changed

+51
-76
lines changed

examples/directRegisterControl/directRegisterControl.ino

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -100,9 +100,9 @@
100100
motorSet(1, LL_HH, 50);
101101
delay(1000);
102102

103-
Serial.print("backward / forward ");
103+
Serial.println("backward / forward ");
104104
motorSet(0, LL_HH, 255);
105105
motorSet(1, HH_LL, 255);
106106
delay(1000);
107107

108-
}
108+
}

library.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
"url":"https://www.infineon.com/cms/en/product/power/motor-control-ics/brushed-dc-motor-driver-ics/multi-half-bridge-ics/",
1313
"maintainer": true
1414
},
15-
"version":"4.2.0",
15+
"version":"4.2.1",
1616
"license":"MIT",
1717
"frameworks":"arduino",
1818
"platforms":[

library.properties

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
name=multi-half-bridge
2-
version=4.2.0
2+
version=4.2.1
33
author=Infineon Technologies
44
maintainer=Infineon Technologies <www.infineon.com>
55
sentence=Library of Infineon Multi Half-Bridge IC controllers family

src/spic-arduino.cpp

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
* This function is setting the basics for a SPIC and the default spi.
1515
*
1616
*/
17-
SPICIno::SPICIno() : lsb(LSBFIRST), mode(SPI_MODE1), clock(SPEED)
17+
SPICIno::SPICIno(): clock(SPEED)
1818
{
1919
spi = &SPI;
2020
}
@@ -28,10 +28,8 @@ SPICIno::SPICIno() : lsb(LSBFIRST), mode(SPI_MODE1), clock(SPEED)
2828
* @param mode SPI mode
2929
* @param clock SPI clock divider
3030
*/
31-
SPICIno::SPICIno(uint8_t lsb, uint8_t mode, uint32_t clock) : lsb(LSBFIRST), mode(SPI_MODE1), clock(SPEED)
31+
SPICIno::SPICIno(uint32_t clock): clock(SPEED)
3232
{
33-
this->lsb = lsb;
34-
this->mode = mode;
3533
this->clock = clock;
3634
spi = &SPI;
3735
}
@@ -48,7 +46,7 @@ SPICIno::SPICIno(uint8_t lsb, uint8_t mode, uint32_t clock) : lsb(LSBFIRST), mod
4846
* @param mosiPin mosi pin number
4947
* @param sckPin systemclock pin number
5048
*/
51-
SPICIno::SPICIno(SPIClass &port, uint8_t csPin, uint8_t misoPin, uint8_t mosiPin, uint8_t sckPin) : lsb(LSBFIRST), mode(SPI_MODE1), clock(SPEED)
49+
SPICIno::SPICIno(SPIClass &port, uint8_t csPin, uint8_t misoPin, uint8_t mosiPin, uint8_t sckPin): clock(SPEED)
5250
{
5351
this->csPin = csPin;
5452
this->misoPin = misoPin;
@@ -68,14 +66,14 @@ SPICIno::SPICIno(SPIClass &port, uint8_t csPin, uint8_t misoPin, uint8_t mosiPin
6866
Error_t SPICIno::init()
6967
{
7068
spi->begin();
71-
spi->beginTransaction(SPISettings(SPEED, this->lsb, this->mode));
69+
spi->beginTransaction(SPISettings(SPEED, LSBFIRST, SPI_MODE1));
7270
return OK;
7371
}
7472

7573
/**
7674
* @brief Deinitialize the SPIC
7775
*
78-
* This function is deinitializing the chosen spi channel.
76+
* This function deinitialize the chosen spi channel.
7977
*
8078
* @return Error_t
8179
*/

src/spic-arduino.hpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -36,13 +36,11 @@ class SPICIno: virtual public SPIC
3636
uint8_t mosiPin;
3737
uint8_t sckPin;
3838
SPIClass *spi;
39-
uint8_t lsb;
40-
uint8_t mode;
4139
uint32_t clock;
4240

4341
public:
4442
SPICIno();
45-
SPICIno(uint8_t lsb, uint8_t mode, uint32_t clock);
43+
SPICIno(uint32_t clock);
4644
SPICIno(SPIClass &port, uint8_t csPin, uint8_t misoPin=MISO, uint8_t mosiPin=MOSI, uint8_t sckPin=SCK);
4745
~SPICIno();
4846
Error_t init();

src/tle94112-platf-ino.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
/*!
2727
* Standard chip select pin for first TLE94112 shield
2828
*/
29-
#define TLE94112_PIN_CS1 10
29+
#define TLE94112_PIN_CS1 SS
3030

3131
/*!
3232
* Standard chip select pin for second TLE94112 shield

src/tle94112.cpp

Lines changed: 40 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,19 @@
1313

1414
using namespace tle94112;
1515

16+
/*! \brief SPI address commands */
17+
#define TLE94112_CMD_WRITE 0x80;
18+
#define TLE94112_CMD_CLEAR 0x80;
19+
1620
#define TLE94112_STATUS_INV_MASK (Tle94112::TLE_POWER_ON_RESET)
1721

22+
/*! \brief time in milliseconds to wait for chipselect signal raised */
23+
#define TLE94112_CS_RISETIME 2
24+
25+
/*! \brief micro rise time to wait for chipselect signal raised */
26+
#define TLE94112_CS_MICRO_RISETIME 150
27+
28+
1829
Tle94112::Tle94112(void)
1930
{
2031
sBus = NULL;
@@ -114,20 +125,9 @@ void Tle94112::_configHB(uint8_t hb, uint8_t state, uint8_t pwm, uint8_t activeF
114125

115126
TLE94112_LOG_MSG(__FUNCTION__);
116127

117-
uint8_t reg = mHalfBridges[hb].stateReg;
118-
uint8_t mask = mHalfBridges[hb].stateMask;
119-
uint8_t shift = mHalfBridges[hb].stateShift;
120-
writeReg(reg, mask, shift, state);
121-
122-
reg = mHalfBridges[hb].pwmReg;
123-
mask = mHalfBridges[hb].pwmMask;
124-
shift = mHalfBridges[hb].pwmShift;
125-
writeReg(reg, mask, shift, pwm);
126-
127-
reg = mHalfBridges[hb].fwReg;
128-
mask = mHalfBridges[hb].fwMask;
129-
shift = mHalfBridges[hb].fwShift;
130-
writeReg(reg, mask, shift, activeFW);
128+
writeReg(mHalfBridges[hb].stateReg, mHalfBridges[hb].stateMask, mHalfBridges[hb].stateShift, state);
129+
writeReg(mHalfBridges[hb].pwmReg, mHalfBridges[hb].pwmMask, mHalfBridges[hb].pwmShift, pwm);
130+
writeReg(mHalfBridges[hb].fwReg, mHalfBridges[hb].fwMask, mHalfBridges[hb].fwShift, activeFW);
131131
}
132132

133133
void Tle94112::configPWM(PWMChannel pwm, PWMFreq freq, uint8_t dutyCycle)
@@ -140,15 +140,8 @@ void Tle94112::_configPWM(uint8_t pwm, uint8_t freq, uint8_t dutyCycle)
140140

141141
TLE94112_LOG_MSG(__FUNCTION__);
142142

143-
uint8_t reg = mPwmChannels[pwm].freqReg;
144-
uint8_t mask = mPwmChannels[pwm].freqMask;
145-
uint8_t shift = mPwmChannels[pwm].freqShift;
146-
writeReg(reg, mask, shift, freq);
147-
148-
reg = mPwmChannels[pwm].dcReg;
149-
mask = mPwmChannels[pwm].dcMask;
150-
shift = mPwmChannels[pwm].dcShift;
151-
writeReg(reg, mask, shift, dutyCycle);
143+
writeReg(mPwmChannels[pwm].freqReg, mPwmChannels[pwm].freqMask, mPwmChannels[pwm].freqShift, freq);
144+
writeReg(mPwmChannels[pwm].dcReg, mPwmChannels[pwm].dcMask, mPwmChannels[pwm].dcShift, dutyCycle);
152145
}
153146

154147
uint8_t Tle94112::setLedMode(HalfBridge hb, uint8_t active)
@@ -196,10 +189,7 @@ uint8_t Tle94112::_getHBOverCurrent(uint8_t hb)
196189
{
197190
TLE94112_LOG_MSG(__FUNCTION__);
198191

199-
uint8_t reg = mHalfBridges[hb].ocReg;
200-
uint8_t mask = mHalfBridges[hb].ocMask;
201-
uint8_t shift = mHalfBridges[hb].ocShift;
202-
return readStatusReg(reg, mask, shift);
192+
return readStatusReg(mHalfBridges[hb].ocReg, mHalfBridges[hb].ocMask, mHalfBridges[hb].ocShift);
203193
}
204194

205195
uint8_t Tle94112::getHBOpenLoad(HalfBridge hb)
@@ -211,10 +201,7 @@ uint8_t Tle94112::_getHBOpenLoad(uint8_t hb)
211201
{
212202
TLE94112_LOG_MSG(__FUNCTION__);
213203

214-
uint8_t reg = mHalfBridges[hb].olReg;
215-
uint8_t mask = mHalfBridges[hb].olMask;
216-
uint8_t shift = mHalfBridges[hb].olShift;
217-
return readStatusReg(reg, mask, shift);
204+
return readStatusReg(mHalfBridges[hb].olReg, mHalfBridges[hb].olMask, mHalfBridges[hb].olShift);
218205
}
219206

220207
void Tle94112::clearErrors()
@@ -235,39 +222,39 @@ void Tle94112::init(void)
235222
TLE94112_LOG_MSG(__FUNCTION__);
236223

237224
//!< initial control register configuration
238-
mCtrlRegAddresses[static_cast<int>(Tle94112::HB_ACT_1_CTRL)] = 0x03;
225+
mCtrlRegAddresses[HB_ACT_1_CTRL] = REG_ACT_1;
226+
mCtrlRegAddresses[HB_ACT_2_CTRL] = REG_ACT_2;
227+
mCtrlRegAddresses[HB_ACT_3_CTRL] = REG_ACT_3;
228+
mCtrlRegAddresses[HB_MODE_1_CTRL] = REG_MODE_1;
229+
mCtrlRegAddresses[HB_MODE_2_CTRL] = REG_MODE_2;
230+
mCtrlRegAddresses[HB_MODE_3_CTRL] = REG_MODE_3;
231+
mCtrlRegAddresses[PWM_CH_FREQ_CTRL] = REG_PWM_CH_FREQ;
232+
mCtrlRegAddresses[PWM1_DC_CTRL] = REG_PWM_DC_1;
233+
mCtrlRegAddresses[PWM2_DC_CTRL] = REG_PWM_DC_2;
234+
mCtrlRegAddresses[PWM3_DC_CTRL] = REG_PWM_DC_3;
235+
mCtrlRegAddresses[FW_OL_CTRL] = REG_FW_OL;
236+
mCtrlRegAddresses[FW_CTRL] = REG_FW_CTRL;
239237
mCtrlRegData[HB_ACT_1_CTRL] = 0;
240-
mCtrlRegAddresses[HB_ACT_2_CTRL] = 0x43;
241238
mCtrlRegData[HB_ACT_2_CTRL] = 0;
242-
mCtrlRegAddresses[HB_ACT_3_CTRL] = 0x23;
243239
mCtrlRegData[HB_ACT_3_CTRL] = 0;
244-
mCtrlRegAddresses[HB_MODE_1_CTRL] = 0x63;
245240
mCtrlRegData[HB_MODE_1_CTRL] = 0;
246-
mCtrlRegAddresses[HB_MODE_2_CTRL] = 0x13;
247241
mCtrlRegData[HB_MODE_2_CTRL] = 0;
248-
mCtrlRegAddresses[HB_MODE_3_CTRL] = 0x53;
249242
mCtrlRegData[HB_MODE_3_CTRL] = 0;
250-
mCtrlRegAddresses[PWM_CH_FREQ_CTRL] = 0x33;
251243
mCtrlRegData[PWM_CH_FREQ_CTRL] = 0;
252-
mCtrlRegAddresses[PWM1_DC_CTRL] = 0x73;
253244
mCtrlRegData[PWM1_DC_CTRL] = 0;
254-
mCtrlRegAddresses[PWM2_DC_CTRL] = 0x0B;
255245
mCtrlRegData[PWM2_DC_CTRL] = 0;
256-
mCtrlRegAddresses[PWM3_DC_CTRL] = 0x4B;
257246
mCtrlRegData[PWM3_DC_CTRL] = 0;
258-
mCtrlRegAddresses[FW_OL_CTRL] = 0x2B;
259247
mCtrlRegData[FW_OL_CTRL] = 0;
260-
mCtrlRegAddresses[FW_CTRL] = 0x6B;
261248
mCtrlRegData[FW_CTRL] = 0;
262249

263250
//!< status register configuration
264-
mStatusRegAddresses[SYS_DIAG1] = 0x1B;
265-
mStatusRegAddresses[OP_ERROR_1_STAT] = 0x5B;
266-
mStatusRegAddresses[OP_ERROR_2_STAT] = 0x3B;
267-
mStatusRegAddresses[OP_ERROR_3_STAT] = 0x7B;
268-
mStatusRegAddresses[OP_ERROR_4_STAT] = 0x07;
269-
mStatusRegAddresses[OP_ERROR_5_STAT] = 0x47;
270-
mStatusRegAddresses[OP_ERROR_6_STAT] = 0x27;
251+
mStatusRegAddresses[SYS_DIAG1] = REG_SYS_DIAG;
252+
mStatusRegAddresses[OP_ERROR_1_STAT] = REG_ERR1;
253+
mStatusRegAddresses[OP_ERROR_2_STAT] = REG_ERR2;
254+
mStatusRegAddresses[OP_ERROR_3_STAT] = REG_ERR3;
255+
mStatusRegAddresses[OP_ERROR_4_STAT] = REG_ERR4;
256+
mStatusRegAddresses[OP_ERROR_5_STAT] = REG_ERR5;
257+
mStatusRegAddresses[OP_ERROR_6_STAT] = REG_ERR6;
271258

272259
//!< bit masking for all halfbridges
273260
mHalfBridges[TLE_NOHB] = { HB_ACT_1_CTRL, 0x00, 0, HB_MODE_1_CTRL, 0x00, 0, FW_OL_CTRL, 0x00, 0, OP_ERROR_1_STAT, 0x00, 0, OP_ERROR_4_STAT, 0x00, 0 };
@@ -292,14 +279,6 @@ void Tle94112::init(void)
292279

293280
}
294281

295-
/*! \brief SPI address commands */
296-
#define TLE94112_CMD_WRITE 0x80;
297-
#define TLE94112_CMD_CLEAR 0x80;
298-
299-
#define TLE94112_STATUS_INV_MASK (Tle94112::TLE_POWER_ON_RESET)
300-
301-
/*! \brief time in milliseconds to wait for chipselect signal raised */
302-
#define TLE94112_CS_RISETIME 2
303282

304283
void Tle94112::directWriteReg(uint8_t reg, uint8_t data)
305284
{
@@ -313,7 +292,7 @@ void Tle94112::directWriteReg(uint8_t reg, uint8_t data)
313292
sBus->transfer(address, byte0);
314293
sBus->transfer(data, byte1);
315294
cs->enable();
316-
timer->delayMilli(TLE94112_CS_RISETIME);
295+
timer->delayMicro(TLE94112_CS_MICRO_RISETIME);
317296
}
318297

319298
void Tle94112::writeReg(uint8_t reg, uint8_t mask, uint8_t shift, uint8_t data)
@@ -354,7 +333,7 @@ uint8_t Tle94112::readStatusReg(uint8_t reg, uint8_t mask, uint8_t shift)
354333
sBus->transfer(address,byte0);
355334
sBus->transfer(0xFF,received);
356335
cs->enable();
357-
timer->delayMilli(TLE94112_CS_RISETIME);
336+
timer->delayMicro(TLE94112_CS_MICRO_RISETIME);
358337

359338
received = (received & mask) >> shift;
360339

@@ -374,5 +353,5 @@ void Tle94112::clearStatusReg(uint8_t reg)
374353
sBus->transfer(address,byte0);
375354
sBus->transfer(0,byte1);
376355
cs->enable();
377-
timer->delayMilli(TLE94112_CS_RISETIME);
356+
timer->delayMicro(TLE94112_CS_MICRO_RISETIME);
378357
}

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