Skip to content

Commit feb61f5

Browse files
committed
[Target] Prevent copying in loop variables (NFC)
/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2769:19: error: loop variable '[Reg, N]' creates a copy from type 'std::pair<unsigned int, llvm::SDValue> const' [-Werror,-Wrange-loop-construct] for (const auto [Reg, N] : RegsToPass) { ^ /llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2769:8: note: use reference type 'std::pair<unsigned int, llvm::SDValue> const &' to prevent copying for (const auto [Reg, N] : RegsToPass) { ^~~~~~~~~~~~~~~~~~~~~ & /llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2954:19: error: loop variable '[Reg, N]' creates a copy from type 'std::pair<unsigned int, llvm::SDValue> const' [-Werror,-Wrange-loop-construct] for (const auto [Reg, N] : RegsToPass) ^ /llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:2954:8: note: use reference type 'std::pair<unsigned int, llvm::SDValue> const &' to prevent copying for (const auto [Reg, N] : RegsToPass) ^~~~~~~~~~~~~~~~~~~~~ & 2 errors generated.
1 parent 5ea29f7 commit feb61f5

File tree

3 files changed

+5
-5
lines changed

3 files changed

+5
-5
lines changed

llvm/lib/Target/ARM/ARMFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1701,7 +1701,7 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
17011701
.addReg(ARM::SP)
17021702
.setMIFlags(MachineInstr::FrameSetup)
17031703
.add(predOps(ARMCC::AL));
1704-
for (const auto [Reg, Kill] : Regs)
1704+
for (const auto &[Reg, Kill] : Regs)
17051705
MIB.addReg(Reg, getKillRegState(Kill));
17061706
} else if (Regs.size() == 1) {
17071707
BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP)

llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2766,7 +2766,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
27662766
// Build a sequence of copy-to-reg nodes chained together with token chain
27672767
// and flag operands which copy the outgoing args into the appropriate regs.
27682768
SDValue InGlue;
2769-
for (const auto [Reg, N] : RegsToPass) {
2769+
for (const auto &[Reg, N] : RegsToPass) {
27702770
Chain = DAG.getCopyToReg(Chain, dl, Reg, N, InGlue);
27712771
InGlue = Chain.getValue(1);
27722772
}
@@ -2951,7 +2951,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
29512951

29522952
// Add argument registers to the end of the list so that they are known live
29532953
// into the call.
2954-
for (const auto [Reg, N] : RegsToPass)
2954+
for (const auto &[Reg, N] : RegsToPass)
29552955
Ops.push_back(DAG.getRegister(Reg, N.getValueType()));
29562956

29572957
// Add a register mask operand representing the call-preserved registers.

llvm/lib/Target/X86/X86ISelLoweringCall.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2421,7 +2421,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
24212421
// Build a sequence of copy-to-reg nodes chained together with token chain
24222422
// and glue operands which copy the outgoing args into registers.
24232423
SDValue InGlue;
2424-
for (const auto [Reg, N] : RegsToPass) {
2424+
for (const auto &[Reg, N] : RegsToPass) {
24252425
Chain = DAG.getCopyToReg(Chain, dl, Reg, N, InGlue);
24262426
InGlue = Chain.getValue(1);
24272427
}
@@ -2461,7 +2461,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
24612461

24622462
// Add argument registers to the end of the list so that they are known live
24632463
// into the call.
2464-
for (const auto [Reg, N] : RegsToPass)
2464+
for (const auto &[Reg, N] : RegsToPass)
24652465
Ops.push_back(DAG.getRegister(Reg, N.getValueType()));
24662466

24672467
// Add a register mask operand representing the call-preserved registers.

0 commit comments

Comments
 (0)